Real numbers may be represented in different ways in computer systems. Standards have been developed for floating point representations, including the commonly used double-precision representation. Standards for arithmetic operations carried out on double-precision numbers have also been developed. For example, the IEEE has defined a standard for double-precision arithmetic in the IEEE 754 Standard (Institute of Electrical and Electronics Engineers, Inc., “IEEE Standard For Binary Floating-Point Arithmetic”, Technical Report 754-1985).
Many computers have architectures that implement IEEE double-precision arithmetic in hardware, providing the correctly rounded result for the basic operations of addition, subtraction, multiplication and division (+, −, *, /) In such computers these operations may be carried out for double-precision floating point representations with good performance.
However, double-precision floating point representations are not sufficient for all applications. In particular, where double-precision arithmetic operations are carried out, rounding will frequently occur in calculating a double-precision result. This rounding can occur in calculating intermediate values, as well as in determining the final result. Where intermediate values are rounded, the result of an arithmetic calculation may vary (depending on the rounding that is carried out) or may be unacceptably inaccurate.
An example of an application where the execution of a long series of floating-point computations produces a result which does not match the correct rounding of the mathematical (i.e., infinitely precise) result is the case of vector dot-product. This is discussed in M. Daumas et al. “Validated roundings of dot products by sticky accumulation”, IEEE Transactions on Computers, 46(5), pp 623-629. May, 1997. The vector dot-product is a basic operation present in many numerical algorithms, including matrix multiply and many other numerical linear algebra computations.
Computer systems are therefore also designed to support an extended-precision floating point representation for real numbers. By using an extended-precision representation unacceptable results due to rounding can be reduced and in some cases avoided. Typically, however, computer systems supporting the extended-precision floating point representation use software implementations to carry out extended-precision arithmetic. The performance (and sometimes accuracy) of these software implementations can be poor. In these cases the processor carrying out the calculation may be carrying out double-precision operations and it is necessary to use software to ensure that the precision available in extended-precision representations is achieved in the operation being executed. For the vector dot-product example referred to above, Daumas et al describe hardware and software support for computing vector dot-products with a tight error bound, at least in most common cases. Other specialized hardware to implement the multiply-add operation include that described in U.S. Pat. No. 4,969,118 (R. K. Montoye et al., “Floating point unit for calculating A=XY+Z having simultaneous multiply and add”), and R. K. Montoye et al. “Design of the IBM RISC System/6000 floating-point execution unit”, IBM Journal of Research & Development, 34(1), pp 59-70, January, 1990. Montoye et al describe a fused multiply-add hardware unit that computes A*B+C as a single atomic operation, producing the correctly rounded mathematical result. The same correctly rounded mathematical results can also be computed with independent multiply and add instruments as described in U.S. Pat. No. 5,880,984 (Mar. 9, 1999, S. M. Burchfiel et al. “Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments”). Other approaches, which compute multiply-add operations as an atomic multiply followed by an atomic add, are referred to in U.S. Pat. No. 5,530,663 (Jun. 25, 1996, L. C. Garcia et al. “Floating point unit for calculating a compound instruction A+B×C in two cycles”) and in U.S. Pat. No. 4,841,467 (Jun. 20, 1989, C. -Y. Ho et al. “Architecture to implement floating point multiply/accumulate operations”).
The most direct approach to improving the accuracy of numerical algorithms with extensive floating-point computations is to increase the number of bits used to represent the mantissa of floating-point numbers. Instances of floating-point hardware that use extended-(80-bit) and quad-precision (128-bit) representations of floating-point numbers are described in U.S. Pat. No. 5,481,686 (Jan. 2, 1996, K. A. Dockser, “Floating-point processor with apparent-precision based selection of execution-precision”), U.S. Pat. No. 5,631,859 (May 20, 1997, P. Markstein et al. “Floating point arithmetic unit having logic for quad precision arithmetic”), and U.S. Pat. No. RE33,629. (Jul. 2, 1991, J. F. Palmer et al. “Numeric data processor”). However, as discussed in M. Daumas et al. “Validated roundings of dot products by sticky accumulation”, IEEE Transactions on Computers, 46(5), pp 623-629. May, 1997, simply increasing the number of bits of the mantissa does not necessarily result in a highly accurate result.
The importance of high-accuracy and exact numerical computations has been recognised, for example in J. H. Bleher et al. “ACRITH: High-accuracy arithmetic, an advanced tool for numerical computation”. Proceedings of the 7th Symposium on Computer Arithmetic, pp 318-321, Urbana, Ill., Jun. 4-6, 1985. Bleher et al describe ACRITH, a commercial product for high-accuracy numerical computation. Methods for exact floating-point computation of sums or differences are discussed in W. E. Ferguson, Jr. “Exact computation of a sum or difference with applications to argument reduction.” Proceedings of the 12 Symposium on Computer Arithmetic, pp 216-221. Bath, England, Jul. 19-21, 1995. Algorithms for arbitrary precision floating point arithmetic are described in D. M. Priest. “Algorithms for arbitrary precision floating point arithmetic”. Proceedings of the 10th Symposium on Computer Arithmetic, pp 132-143. Grenoble, France, Jun. 26-28, 1991.
Although specially designed processors and related software exist to handle extended-precision arithmetic, the cost to redesign existing processors to implement extended precision arithmetic may be prohibitive. It is therefore desirable to have a processor for carrying out extended-precision arithmetic operations that is similar to existing processor designs and which will integrate easily with existing processors but which will permit the implementation of such operations in the processor rather than through software alone.